1. Field of the Invention
The invention relates to a direct memory access (DMA) device, and more particularly to a virtual first in first out (FIFO) DMA device.
2. Description of the Related Art
Referring to FIG. 1, a block diagram of a conventional electronic device during UART transmission. To transmit a first data through a UART unit 110, the higher layer software task 102 firstly calls a UART driver and makes the UART driver fill the first data into a buffer 104, which can be a ring buffer or a double buffer. When the first data has been completely filled into the buffer 104, the UART driver updates a buffer pointer set by the UART driver to a next address. Through the DMA unit 106, the first data stored in the buffer 104 is transferred to and stored in the UART first in first out (FIFO) unit, wherein the UART unit 110 serially outputs the first data. Here, the data transfer between the buffer 104 and the UART FIFO unit 108 can be performed by either the DMA unit 106 or a processor. Normally, the DMA unit 106 is more efficient in transferring data.
In a complicated electronic device, however, it is possible that multiple higher software layer tasks 102A and interrupt service routines (ISR) 112 might use the same UART unit 110 to transmit data, as shown in FIG. 2. Under such circumstance, the data stored in the buffer 104 might be overwritten, resulting in data error. If the ISR 112 has a second data that needs to be transmitted by the UART unit 110 when the first data of the higher layer software task 102A is being filled into the buffer 104, the ISR 112 calls the UART driver to store the second data into the buffer 104. Not until the first data of the higher layer software task 102A has been completely filled into the buffer 104 does the UART driver start to update the buffer pointer. Consequently, the second data is written into the buffer 104 according to original buffer pointer, and therefore the first data, which has been written in the buffer 104, is overwritten. After the UART driver has written the second data of the ISR 112 into the buffer 104, the higher layer software task 102A continues to write the first data into the buffer 104 and therefore will overwrite part of the second data. Accordingly, data loss between the first data and the second data, written in the buffer 104, will result in data error.
There are two conventional methods of solving the data error in the buffer 104. The first method is disabling the ISR 112 to prevent the occurrence of data error before the higher layer software task 102A starts to call the UART driver. However, since the ISR 112 might need to be executed in real-time, if the system fails to process the ISR 112 promptly, it will cause a system error.
The second method involves the use of two buffers. Referring to FIG. 3, a block diagram of using two buffers for UART transmission is shown. The second data of the ISR 112 is written in the buffer 104A, while the first data of the higher layer software task 102A is written in the buffer 104B. By controlling the multiplexer 114, the first data and the second data are alternately transferred to the UART FIFO unit 108 and are further transmitted out by the UART unit 110. However, this method requires more memory space for the buffer and the control of the UART driver is more complicated.
Apart from data loss and data error that might occur during UART transmission, the conventional electronic device also has several problems during UART reception. Referring to FIG. 4, a block diagram of a conventional electronic device during UART reception. After a UART unit 410 receives a third data, the third data is temporarily stored in a UART FIFO unit 408, and then a DMA unit 406 will transfer the third data to a buffer 404. After the DMA unit 406 has transmitted the data of a pre-set length to the buffer 404, the DMA unit 406 notifies a processor 416 to read the data stored in the buffer 404. For example, whenever the DMA unit 406 transmits data of 500 bytes to the buffer 404, the DMA unit 406 notifies the processor 416 to read the data stored in the buffer 404.
However, since the length of the third data received by the UART unit 410 is unpredictable, the DMA unit 406 is unable to determine whether the third data has been completely received. For example, assume the length of the third data is 700 bytes. After the DMA unit 406 transmits the first 500 bytes of the third data, the DMA unit 406 notifies the processor 416 to read the data stored in the buffer 404. However, after the DMA unit 406 transmits the other 200 bytes of the third data, the DMA unit 406 will not notify the processor 416 to read the data stored in the buffer 404 because the length of received data (200 bytes of the third data) does not reach the pre-set length and the DMA unit 406 can not determine that the third data has been completely received. Therefore, the processor 416 has to periodically detect the status of the UART FIFO unit 408 so as to determine whether the UART FIFO unit 408 is empty (because the data has been moved to buffer 404). Besides, the processor 416 further determines whether the UART FIFO unit 408 has been in the empty status for a predetermined period. If so, it represents that the data has been received completely. At this time, the processor 406 reads the data stored in the buffer 404 to process the data.
Before the processor 416 detects the status of the UART FIFO unit 408, the processor 416 has to disable the DAM unit 406 first to prevent incorrect detection due to the movement of data by the DAM unit 406. Before disabling the DAM unit 406, the UART unit 410 has to be disabled first and sends a signal to notify the transmitting end to cease the transmission of data.
However, if data happens to be transmitted to the UART unit 410 when the DMA unit 406 is being disabled, the DMA unit 406 is unable to transfer data from the UART FIFO unit 408 to the buffer 404. Under this circumstance, the data stored in the UART FIFO unit 408 might overflow, causing data loss. To prevent data loss, a buffer of at least 16 bytes must be reserved for the UART FIFO unit 418.
On the other hand, if the processor 416 is used to transfer data from the UART FIFO unit 408 to the buffer 404, the UART FIFO unit 408 must be enlarged lest the processor 416 might be frequently interrupted in order to process data transferring because the UART FIFO unit 408 is easily filled up. However, this will further increase the cost.
To summarize, during UART transmission, the UART driver of a conventional electronic device might be unable to update the buffer pointer promptly, resulting in data error as parts of data are overwritten. During UART transmission, (1) the processor 416 must periodically detect the status of the buffer 404 and the UART FIFO unit 408, hence reducing the efficiency of the processor 416; (2) when the DMA unit 406 is disabled, an extra buffer of 16 bytes must be reserved for the UART FIFO unit 408 to prevent the UART FIFO unit 408 from data overflow. It will consequently increase the cost and the chip size of the UART FIFO unit 408.